Of key concern in developing Ultra Large Scale Integrated (ULSI) circuits is achieving high performance with increased density within the limits of optical lithography. In this regard, FET and Bipolar devices fabricated on Silicon on Insulator (SOI) have demonstrated significant performance (speed and power) improvement over devices fabricated on silicon substrates and, also, are less sensitive to radiation. This is because silicon devices have problems with inherent parasitic circuit elements due to junction capacitances. One way to avoid this problem is to fabricate silicon devices on an insulating substrate. Hence, the reason for the Silicon on Insulator (SOI) technology is that it offers the highest performance for a given feature size due to minimizing parasitic capacitance. However, such SOI substrates are more costly than silicon substrates because it must be prepared with a buried insulating layer. By some methods of preparation, the buried insulating layer is not defect free. In addition, conventional manufacturing techniques must be modified for fabricating devices using SOI substrates which adds further cost.
In addition, high density devices are difficult to obtain in a planar structure due to limitation of optical lithography resolution. To increase the density of the integrated circuits, the transistors can be formed vertically thereby reducing the active lateral surface area required for the device. Therefore, vertical transistors, such as MOSFETs, have significantly higher packing density of, at least, a factor of 10 over their standard lateral counterparts. However, state of the art vertical MOSFETs have had a very limited application due to the silicon substrate used to fabricate them. When a silicon substrate is used, it acts as a common source or drain for all transistors and, because of this, only one type of vertical MOS transistor has been fabricated on a silicon wafer until recently. By using a silicon on insulator (SOI) wafer, complementary MOS (CMOS) devices have been fabricated in adjacent islands with a common gate formed in a trench between the adjacent complementary MOS devices. However, in this process, the starting point is a SOI wafer in which the source or drain are formed in the silicon above the insulating layer followed by an epitaxical deposition of a silicon layer. Such a process prevents interconnecting the buried source and drain between the islands.
Bipolar integrated circuits, of course, provide higher speed operation and greater drive currents than the FET circuits. Further, the integration of FET and bipolar transistors on a single substrate has become highly desirable. However, SOI substrates predominately have been used in fabricating FETs, such as CMOS, because bipolar or biFET processes on SOI substrates have resulted in defect density problems caused by the buried insulating layer not being as defect free.